The present invention relates to a logic verification method for semiconductor devices, and, more particularly, to a logic verification method for semiconductor devices which have logics described hierarchically.
In designing semiconductor devices, such as Large Scale Integration (LSI), the operation of logic-described circuits is verified by logic simulation. In general, the logics of an LSI are described hierarchically by a hardware description language (HDL). The recent trend is toward production of system LSIs that achieve system level functions on a single chip. In a system LSI, logics are described for each of various functional macros, and logics, which show the connection relationship among the functional macros.
Logic verification of an LSI is executed using a logic simulator. The logic simulator provides LSI logics with various kinds of input signal values and compare output signal values corresponding to the input signal values with expected values for normal logic operations of the LSI to check if they match one another.
At the time of verifying the LSI logics, it is necessary to produce logics described hierarchically beforehand. Specifically, in a case where there is a lower-hierarchy logic to be logically combined (connected) with an upper-hierarchy logic to be verified, the upper-hierarchy logic and lower-hierarchy logic descriptions are needed. Even if an upper-hierarchy logic (interconnection logic among individual functional macros) is to be verified, for example, verification cannot be done unless without all of the lower-hierarchy logics. In a case where any lower-hierarchy logic has not been produced, which is associated with logic to be verified, it is necessary to prepare a pseudo operational model for that lower-hierarchy logic.
As mentioned above, verification of upper-hierarchy logic involves lower-hierarchy logics which are not the verification target. This makes the verification time (logic simulation execution time) longer. Since a logic simulator stores lower-hierarchy logics in a memory, the amount of memory occupation increases at the time of logic verification. This slows down the logic verification execution, thus resulting in a lower efficiency of logic verification. Further, in the case of verifying logics including a lower-hierarchy logic which is not the verification target, input signal values, which are combinations of various signals, should be generated in order to acquire arbitrary output signal values from that lower-hierarchy logic. This further reduces the efficiency of logic verification.